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EMC Suppression Concepts for Printed Circuit Boards

Routing Clock Traces

    This article discusses how to route traces on a printed circuit board (PCB), along with proper component placement. We must be concerned with both the time domain (functionality), and frequency domain (EMI) of any product design. The discussion is applicable to single-sided, double-sided, and multilayer designs.
    Oscillators, associated components, and clock traces account for a significant amount of the RF energy generated within a PCB. A clock circuit is defined as the functional area that physically contains the oscillator and/or its buffers, drivers, and associated components, both active and passive. RF energy is observed related to both the rise and fall time of signal transitions, and the fundamental clock frequency of active components. To determine the highest RF spectral distribution of energy typically observed, Equation 1 is used. This equation does not take into account harmonics of the primary frequency.

Eq. 1 (Eq. 1)

where fmax = maximum generated RF frequency, and tr = edge rate in ns (use the faster value of either the rise or fall time).
    For example, a 2 ns edge rate, typical of common clock drivers and components, can be expected to radiate significant RF energy up to 160 MHz, falling off rapidly above that frequency. The possible significant RF spectrum is 10 fmax or 1.6 GHz, which includes the harmonic content of the main frequency component.
    Clock and periodic signal traces should always be manually routed before any other action occurs. Following successful manual routing of clocks and sensitive or high-threat traces rich in RF energy, the rest of the PCB can be routed by automatic means.

Component Placement

    Locate clock generation components near the center of the PCB, or adjacent to a mechanical ground stitch location (to chassis ground), rather than along the perimeter of the board or near the I/O section. If the clock trace goes off the board to a daughter card, ribbon cable, or interconnect, locate the clock circuit some distance from this interconnect, but not so far away as to make the interconnect trace electrically long. Terminate the clock trace directly at the connector, whether an interconnect is present or not. It is imperative that this be comprised of a single point-to-point connection. Termination of clock lines where a trace crosses a boundary (connector) guarantees signal quality and improves functional performance. Without termination, a clock trace can act as a monopole antenna when no interconnect, or load, is provided. In addition, proper termination of transmission lines helps suppress common-mode induced RF currents from coupling into other areas susceptible to RF corruption. Install oscillators and crystals directly on the PCB rather than using sockets. Sockets add lead length inductance (LdI/dt). Lead length inductance allows ground noise voltage to be created across the transmission line. Ground noise voltage is developed because there may exist a difference in voltage potential between two circuits, caused by inductance in the circuit. Ground noise voltage in turn generates common-mode RF currents, which can radiate, or couple, into susceptible areas.

Trace Lengths

    Locate components that use clocks or periodic signals to achieve the shortest, straight-line path possible (minimal Manhattan length) between two points, with no vias in the trace route, if possible. Ground vias, if required, are discussed later in this article. Each via adds approximately 1–3 nH inductance to the trace route. Inductance in a trace can cause both signal quality concerns (time domain) and potential RF emissions (frequency domain). The total inductance within a trace is added to the sums of all via inductance. The faster the edge rate of the clock signal, the more this design rule becomes mandatory. If a periodic signal, or clock trace, must traverse from one routing plane to another, this transition should occur only at a component lead at 0V, or ground reference, not anywhere else. The reason for making the transition adjacent to a component lead is to allow RF return current to easily make a layer transition jump. Try for a maximum of two vias per route, one at the source, and one at the load, if a stripline configuration is provided.
    The old directive to "keep clock lines short" will always be valid. The longer the trace, the greater the probability that RF currents will be produced, and more spectral distribution of RF energy created. Clock traces must be terminated to reduce ringing (enhance signal integrity), and to prevent the creation of avoidable RF currents. Improperly terminated clock signals might also degrade the signal to the point of being nonfunctional, depending on frequency of operation and logic family provided.

Determining Electrically Long Trace Lengths

    How do we determine if a trace is electrically long? Typical velocity of propagation of a signal in a trace is 60 % of the speed of light. From this, calculate the maximum permissible un-terminated line length (Eq.2). This equation is valid when the two-way propagation delay (source-load-source) is greater than, or equal to, the signal rise time. This length is for round trip distance. The one way length, from source to load, is 1/2 the value of Lmax.

Eq. 2 (Eq. 2)

where tr = edge rate of the signal transition (ns); t'pd = propagation delay of 1 cm of line (ns); and Lmax = maximum round trip distance of the routed trace (centimeters).
    When dealing with transmission lines, a PCB designer needs a general rule-of-thumb during component placement that allows quick determination of whether a trace route can be considered electrically long. A simple calculation is available with almost absolute accuracy. When determining if a trace is electrically long, think in the time domain, as the propagation speed of the signal is based exclusive on the permittivity, or dielectric constant of the planar material.
    To simplify (Eq. 2), there are two basic equations for determining maximum electrical routed length before termination is required. These equations, (Eq. 3 and 4), take into account conversion from units of feet to cm and include the propagation delay, tpd. For FR-4 material, with a dielectric constant of 4.6, the flight time of a signal routed microstrip is tpd = 1.72 ns/ft and for stripline tpd = 2.2 ns/ft. If the routed trace length is greater than Lmax, both signal functionality and EMI concerns exist.

Lmax = 9 * tr (for microstrip topology – in cm.) (Eq. 3)
Lmax = 3.5 * tr (for microstrip topology – in inches)
Lmax = 7 * tr (for stripline topology – in cm.) (Eq. 4)
Lmax = 2.75 * tr (for microstrip topology – in inches)

For example, if a signal edge is 2 ns, the maximum unterminated trace length for routed microstrip is:

Lmax=9 tr=18 cm (7").

When this same clock trace is routed stripline, the maximum unterminated trace length of this 2 ns signal edge is now:

Lmax=7 tr =14 cm (5.5").

    For materials with a dielectric constant other than 4.6, the propagation delay of a signal within a trace will differ. To use a different dielectric constant value, (Eq. 5) is presented.

Eq. 5 (Eq. 5)

where: a=30.5 (for cm) or 12 (for inches); and x=0.5 (converts transmission line to one way path). The equations for propagation delay of a signal are for microstrip, and for stripline, with e r the dielectric constant of the material at the frequency of operation. For example, if e r = 4.1, Lmax=8.9 cm (3.5 in.) for microstrip, and 6.9 cm (2.7 in.) for stripline.
    If a trace is longer than Lmax, termination is required, as signal integrity concerns, reflections and ringing may occur. Ringing generated by an impedance mismatch in an electrically long trace may also make the circuit nonfunctional, and could create common-mode RF currents within the trace. (The signal of interest is usually differential mode.) Even with optimal termination, a finite amount of RF current will exist in the trace due to the potential difference between the source and load circuit.
    For every signal, a time domain reflection occurs. It takes a finite time for a signal to travel from source-to-load, and then return from load-to-source. An electrically long trace is a trace that allows the one way (source-to-load) propagation delay to exceed 1/2 the clock cycle. If a second clock signal (edge transition) occurs before the reflection of the original signal returns to the source, signal integrity problems occur. Depending on the phasing of the reflection, overshoot or undershoot may develop, which affects signal integrity. Signal degradation is a concern if the edge time of the signal constitutes a significant percentage of the propagation time between the device load intervals. Proper termination prevents ringing and reflections from occurring, thus enhancing signal functionality.

Routing Layers for Clock Traces

When designing any PCB, one must take into consideration several major concerns. These concerns relate to optimal signal integrity along with EMC compliance.

  1. Creating a transmission line with proper terminations for all critical traces.

  2. Minimizing inductance within the transmission line structure.

  3. Providing a return path for RF currents using the lowest impedance path possible. (Refer to Issue No. 173, Spring, 1997 of this newsletter for a discussion of RF return currents.)

   For single- and double-sided PCBs, it is virtually impossible to create an optimal transmission line. The impedance of a typical trace on a single- or double-sided PCB is 110 to 135 ohms. When used in a 50 ohm circuit, this impedance mismatch may cause the system to become nonfunctional, especially if the system clock is greater than 10 MHz, or clock edges are faster than 5 ns. In addition, an optimal RF return path may not be present in a single-sided design, whereas in a double-sided assembly, the distance between the trace and the RF return path is excessively large, typically 0.16 cm (0.062").
    RF flux present on a trace is generally observed at a distance that is equal to the width of the trace. RF flux from a 0.008" trace will couple easily to an image plane that is 0.008" away, instead of a plane 0.062" away. Because of the current density distribution of RF flux, related to a RF return path, use of single- or double-sided PCBs is not recommended for any high-speed design. Figure 1 illustrates RF field distribution for microstrip traces. For a double-sided PCB, RF flux must travel through a dielectric material to find the RF return path. If a trace at 0V potential is routed adjacent to the clock trace on a single-side design (coplanar configuration), the trace becomes the RF return path. There is no simple technique for routing single- and double-sided PCBs that are EMI compliant due to: lack of an optimal RF return path, high trace impedance, and lack of a proper transmission line. Although use of a simple stackup assignment is cost effective, additional cost will probably be required through use of shielding or containment of internally created RF energy. It is generally cheaper to add a power and ground plane to a PCB, than to rely on secondary shielding methods.


Figure 1

    For multilayer designs, clocks and periodic signals must be routed adjacent to a solid plane, preferably at ground or 0V potential. A plane must not be floating or isolated. This is true for both routing layers, "x" axis and "y" axis (also identified as the horizontal or vertical routing planes). When selecting routing layers, the designer must be concerned with which layers to use for trace routing, jumping between designated layers, and maintaining constant trace impedance.
    Figure 2 shows an example of how to optimally route clock traces on different layers, assuming a multilayer stackup. The following design guidelines are suggested:

1. A solid (image) plane is located adjacent to the routing plane, or signal trace. Minimize routed trace a vertical length while maintaining constant trace impedance of the transmission line. If series termination is provided, connect the resistor directly to the output pin of the component. After the resistor, place a via to the internal stripline layer(s). The use of ground planes is preferred over use of voltage planes for the following reason: Voltage planes generally contain switching noise injected by components into the power distribution system. The voltage plane may disrupt the RF return path or cause common-mode coupling of switching noise into the RF return path.

2 Do not route clock or sensitive traces on the outer layers of a multilayer board, if a six or more layer stackup is provided. The outer layers of the PCB should be reserved for large signal busses and I/O circuitry. Functionality and signal quality of these traces could be corrupted by routing high-threat signals microstrip. When routing traces between layers, there will be a change in the characteristic impedance of the trace, as the trace relates to a reference plane (impedance control), thus affecting performance and possibly causing signal degradation.
    If the design maintains constant trace impedance, provides for an optimal RF return path, and minimizes or eliminates use of vias (reduce inductance), the trace will not radiate any more than a coax.


figur2 Figure 2



Figure 3

Layer Jumping (Use of Ground Vias)

    When routing clocks or high-threat signals, it is common practice to via the trace between routing planes (e.g., x-axis) and then via this same trace to another plane (e.g., y-axis) from source to load. This is shown in the poor routing method of Figure 2. It is generally assumed that if each and every trace is routed adjacent to an image plane, or RF return path, there will exist tight RF coupling (flux cancellation) of common-mode RF currents along the entire route. In reality, this assumption is incorrect.
    When a jump is made from a horizontal to routing layer, the RF return current cannot make this jump. This is because a discontinuity occurs in the trace route by the vias. The RF return current must now find an alternate, low inductance (impedance) path to complete its return. A suitable alternate path usually does not exist when jumping a trace between layers. To minimize creation of EMI and crosstalk, due to layer jumping, the following design techniques have been found to be effective:

    A ground via is a via that is placed directly adjacent to each signal route via at one trace width distance away. Ground vias can only by used when there are multiple ground planes in the PCB. This via must connect all ground planes together. Ground vias guarantee that a constant RF return path is adjacent to a signal route, thus providing a mechanism for optimal flux cancellation. The ground pin of a component makes an excellent ground via.
    For a four-layer PCB, with one voltage plane and one ground plane, how is a constant RF return path provided when a ground via cannot be used? To maintain a constant return path for RF currents, the 0V reference plane must be allowed to act as the primary return path. When the trace must route against the power plane, use of a ground trace is required, with vias at both ends of the ground trace routed parallel, and adjacent, to the signal trace tied to the 0V reference plane. Using this configuration, a constant RF return path can now be maintained, as detailed in Figure 3.


The important concept for routing traces with periodic signals is to provide a properly terminated, impedance controlled signal route adjacent to a RF return image plane. This image plane provides for flux cancellation of RF common-mode currents, and allows the trace to function as a coaxial transmission line. Ground vias allow the RF return path to be undisturbed along the entire trace route. If multiple ground planes are not provided, a ground trace must be used on the routing plane adjacent to the signal trace to assure a constant, undisturbed RF return path.

Mark I. Montrose writes this.